To reduce power consumption in mobile communications equipment, it is frequently desirable to provide for a standby or idle mode of operation. During standby mode, the equipment is active only during short intervals when listening for a page, and is powered down during the remaining intervals. It is important to maintain accurate system timing to ensure that the equipment is active during precisely the correct intervals. It is also highly desirable to reduce the power consumption of the equipment as much as possible in the standby or idle mode.
To maintain system timing in a typical GSM communication device, a clock having a relatively high degree of accuracy (e.g., 1 ppm) is provided which is active at all times, including during standby. Such clocks can consume relatively large amounts of power. An exemplary clock used in mobile phones is a voltage controlled crystal oscillator (VCXO) which runs at, e.g., 13 MHz. In addition, a mobile phone may also have a simple low-power real time clock (RTC) for showing time on a communications device display. This clock runs at a much lower frequency (32.768 kHz) and is typically not very accurate (e.g., 10-20 ppm, depending upon the quality of the clock crystal).
It would therefore be desirable to reduce the power consumption of communications equipment operating in a standby mode by switching the high frequency, high current clock off, yet maintain accurate system timing.
U.S. Pat. No. 5,493,700 to Hietala et al. (Hietala '700) discloses an automatic frequency control (AFC) apparatus for a radiotelephone. The radiotelephone includes a transmitter, a receiver, a user interface, control logic, and a synthesizer which provides signals at an appropriate frequency to the transmitter and receiver, and which provides a clock signal to the user interface and control logic. The control logic controls the frequency of the synthesizer. The synthesizer includes two fractional-N synthesizers and a phase-locked loop. The Hietala '700 patent does not disclose a method for reducing current in a standby mode while maintaining accurate system timing.
U.S. Pat. No. 5,055,802 to Hietala et al. (Hietala '802) discloses a multiaccumulator sigma-delta fractional-N synthesizer which controls the frequency of a voltage controlled oscillator output signal. Relatively small frequency offset increments can be introduced into the synthesizer. The Hietala '802 patent does not disclose a method for reducing current in a standby mode while maintaining accurate system timing.
U.S. Pat. No. 5,070,310 to Hietala et al. (Hietala '310) discloses a multiple latched accumulator fractional N-synthesizer for a digital radio transceiver which avoids data "ripple" through multiple accumulators, and which reduces spurious signals. The Hietala '310 does not disclose a method for reducing current in a standby mode while maintaining accurate system timing.
U.S. Pat. No. 5,331,293 to Shepherd et al. (Shepherd) discloses a digital frequency synthesizer which compensates for spurious signals by demodulating, inverting, and amplifying the synthesizer output to generate a compensation signal which adjusts a reference oscillator. Shepherd does not address the reduction of power consumption by providing for a standby mode while maintaining accurate system timing.
It is known in Pacific Digital Cellular mobile phones to power down a high frequency crystal oscillator and use a second oscillator, which operates at a lower frequency and consumes less power, during an idle mode. In the PDC system, however, the symbol rate is 21 ks/s, which is significantly lower than the 270.833 ks/s in the GSM system. As a result, PDC system timing requirements are significantly less precise than the timing requirements of GSM and other systems, and there is no need for an accurate low frequency oscillator in a PDC system. Thus, the power reduction method in the PDC system is not suitable for GSM or other relatively high bit rate systems having relatively stringent timing requirements.